1. Field of the Invention
The present invention relates to a method of forming a solder bump structure, and more specifically, to a method of forming a parasitic capacitance-preventing dummy solder bump structure.
2. Description of the Prior Art
High performance microelectronic devices often use solder balls or solder bumps for electrically and mechanically interconnection to other microelectronic devices. For instance, a very large scale integration (VLSI) chip may be electrically connected to a circuit board or other next level packaging substrate by using solder balls or solder bumps. This connection technology is also referred to as “Controlled Collapse Chip Connection (C4)” or “flip chip” technology. The flip chip technology is an area array connection technology and includes reflowing a body of solder onto a bond pad to form a solder bump, so as to electrically connect an IC die to a packaging board.
Please refer to FIG. 1 to FIG. 4 of schematic views of forming a solder bump according to the prior art. As shown in FIG. 1, a surface of a substrate 10 comprises a first area 12 and a second area 14, and at least one conductive layer 16 is positioned on the surface of the substrate 10. Normally, the substrate 10 is a semiconductor wafer with circuits formed inside the semiconductor wafer, and the first area 12 and the second area 14 are respectively a central area and a border area of the surface of the substrate 10.
As shown in FIG. 2, a chemical vapor deposition (CVD) process is performed to form a dielectric layer 18 on the substrate 10 to cover the conductive layer 16. An etching process is then performed to form at least one via hole 20 in portions of the dielectric layer 18 within the first area 12 down to a surface of the conductive layer 16. By performing a deposition process, a via plug 22, comprising tungsten, is formed in each via hole 20. A chemical mechanical polishing (CMP) process is performed thereafter to make a top surface of the via plug 22 approximately aligned with a top surface of the dielectric layer 18.
As shown in FIG. 3, a metal pad 24, comprising either copper or aluminum, is formed within each of a plurality of predetermined regions within the first area 12 and the second area 14. A CVD process and an etching process are then performed to form a passivation layer 26 on portions of the dielectric layer 18 not covered by the metal pad 24. As shown in FIG. 4, an under bump metallurgy (UBM) layer 28 is formed on each metal pad 24 by performing a sputtering process and an etching process. Finally, a solder bump 30 is formed on each UBM layer 28. Wherein portions of the solder bumps 30 formed within the second area are employ as dummy solder bumps to make the layout of the solder bumps 30 on the surface of the substrate 10 symmetrical, so as to improve the fluidity of an underfill liquid compound in subsequent packaging processes.
However, as technology progresses, the process line width of semiconductor manufacturing decreases as well. Parasitic capacitance therefore occurs between the metal pad 24 and the conductive layer 16 due to the shortened distance between the metal pad 24 and the conductive layer as the thickness of the dielectric layer 18 is narrowed, leading to the defective electrical performance or even circuit fail of the device.